This invention relates, in general, to semiconductor devices, and more particularly to a method of fabricating a semiconductor structure that is compatible with multiple technologies.
In the semiconductor art, a trend is toward the fabrication of device structures that are compatible with multiple technologies. For example, structures allowing for the implementation of both bipolar and MOS devices in a single integrated circuit are highly desirable because the best characteristics of both technologies may be obtained. This allows for the fabrication of CMOS and BIMOS high performance integrated circuits. For fabrication methods of multiple technology integrated circuits to become practical, process integration flexibility must be obtained. Additionally, it is desirable to be able to develop methods of fabrication having enhanced scalability characteristics.
Prior art methods of fabricating semiconductor structures having variable width shallow isolation elements, especially those disposed over deep trench isolation elements generally require multiple masking steps. Specifically, masks are used to define the encroachment of the isolation elements into the active regions. Inherent with multiple masking steps are misalignment tolerances that must be provided for. These misalignment tolerances prohibit aggressive scaling of structures and require additional real estate.
In view of the above, it would be highly desirable to have a method of fabricating semiconductor structures having variable width shallow isolation elements self-aligned to deep trench isolation elements.